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AMD mini processor: A giant step into the heterogeneous revolution

Improved computer responsiveness is crucial for the development of a modern multi-threaded computer system. However, when we look at the mobile environment where in many cases the core complex needs to remain in a low power or powered off state in order to save power or because of thermal constraints, a clear degradation of the overall responsiveness of the system becomes apparent. In many cases certain tasks that generate such interrupts responsible for awakening the cores are usually GPIO or even low IPC tasks which don’t need a large computational core to process them. In this sense in a heterogeneous paradigm even a tiny core could be enough to address this issue, only waking up the big or little cores as needed by the task request.

Seeking a solution to this challenge AMD has been working on developing some heterogeneous solutions and some recently published patents reveal that the introduction of a tiny x86 processor has the potential to be a giant step toward its heterogeneous revolution.

The AMD x86 mini processor

A block diagram of the proposed task service hierarchy.

Earlier this year a new AMD patent was published proposing a new task service hierarchy that can significantly improve energy savings through gradual engagement of the interrupt service stages, avoiding waking up the more power-hungry cores and other significant circuitry by interrupting tasks that may be handled by an intermediate interrupt service entity. The basic idea of this hierarchical interrupt service is to involve more stages into the task service in a finer granular way, dividing them into a series of stages for interrupts/activity service.

A block diagram describing the multiple stages of the system for efficiently servicing input tasks

The first stage is responsible for serving some of the GPIO/initial service, often resolving so many of these requests at this stage. Once the first stage infers whether a specific task or interrupt service requires access to the main memory or needs a x86 state to run, the second stage is invoked.

Expanding on this second stage, which is directly related to the mini processor proposed, a second patent released just a few days ago reveals precisely some functions of this new x86 mini processor. At this stage the mini processor can interrupt service routine tasks that require x86 instructions, can perform restore tasks such as restoration of an architecture state associated with device configuration registers, restoration of a micro-architectural state required for a device to summarize its execution – or operating system execution – and can perform general purpose low IPC tasks. The mini processor can also warm up the last level cache and fetch code and data into a shared cache between the mini processor and the big processor so that when execution switches to the big processor request misses are avoided. Thus, software, drivers and operating systems may be unaware of any of these transitions making it very efficient in that no additional resources need to be used in the operating system or to execute software to perform the task servicing.

In fact, it’s important to note that this new mini processor is effectively considerably powerful. Even though its functions are limited to a very restricted set of operations, it’s clear that the proposed mini processor is more powerful than a simple microcontroller, probably being very similar to the small energy-efficient ARM core. It is also interesting to note that the proposed mini processor implements a restricted version of the x86 ISA, reinforcing my initial hypothesis that AMD would implement composite x86 ISAs, thus increasing flexibility in creating cores that mix and match specific sets of features, further improving overall performance and energy savings. For more details see my article. [Link]

Finally, if the second stage infers the need for greater computational power to complete the task or if it has insufficient capacity for the proper execution of the task (e.g., Need for some specific instruction), the final stage is invoked and finally the core complex is activated. It is important to note that in the transfer of execution from one stage to the next, interrupts may be routed to a targeted stage, then execution transferred as successive stages are activated, which may occur in parallel or on demand, and that the execution of the task can be transparently passed between different cores.

A tiny processor and a giant step

It was predicted that at some point in this Post Dennard era we would experience a transition from homogeneous to heterogeneous multiprocessing. Among the many steps needed in this great revolution we are about to witness AMD is showing that on its way to pursuing its heterogeneous revolution, subtle but powerful steps can be a more reliable and safer path for introducing new technologies to their processors. The introduction of this mini processor could eventually significantly reduce the power consumption of future Zen generations while at the same time bring greater overall responsiveness to the entire system on both their mobile and desktop platforms.

Although these patents still do not show in greater detail what AMD is developing for its future heterogeneous processors, it is possible to state that the implementation of this mini processor will be a giant step towards this heterogeneous revolution that AMD has been preparing for more than one decade.

Some references and reading recommendations:

  • US20200409762 – Method and apparatus for servicing an interrupt – Branover et al. – AMD [Link]
  • US 20210173715 – Method of task transition between heterogenous processors – Branover et al. – AMD [Link]
  • Underfox – “AMD Master Plan Pt.2 – Heterogeneous Revolution” – Coreteks – 2020 [Link]


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